Today's computer networks handle an ever-increasing amount of data. Fast Ethernet transmits and receives packets at rates of at least 100 Mbps., and other technologies such as asynchronous transfer mode (ATM) also require high data rates.
Very high speed applications traditionally use current-switching technologies known as emitter-coupled logic (ECL) gates and drivers.
CMOS typically operates with a power supply of 5V or 3.3V, but ECL traditionally operates with a negative power supply. Thus, standard ECL levels are not generally compatible with CMOS. A positive-voltage-shifted ECL, known as pseudo-ECL (PECL), has been used for CMOS chips using ECL-type current drivers.
ECL current drivers are often used to drive differential signals. Using a pair of signals rather than just one signal reduces sensitivity to noise and interference, since interference usually affects both signals equally, while not affecting the voltage difference between the two signals, nor the difference in current driven to each signal.
FIGS. 1 and 2 show conventional application circuits of a CMOS-PECL driver. Specifically, FIG. 1 is a schematic representation of a PECL output circuit 1 connecting with a 50.OMEGA.termination resistor 2.
The output DC levels of the circuit of FIG. 1, V.sub.OL and V.sub.OH, are functions of source voltage, V.sub.DD, electron mobility, .mu..sup.p, threshold voltage, V.sub.T and temperature. Estimations from quick calculations show that the variations of both V.sub.OL and V.sub.OH are roughly equivalent to about .+-.600 mV. Variations on V.sub.DD account for about 60% of the output voltage variation and the other 40% is contributed from variations of manufacturing process specifications and temperature.
Therefore, there is a need to develop a new CMOS-PECL driver that delivers a tightly controlled output level under different operating conditions and over wide-tolerance manufacturing process specifications.
FIG. 3 is a detailed circuit diagram of the CMOS-PECL driver circuit 1. Referring to FIG. 3, the output of a phase splitter circuit 4 is connected to a plurality of NAND gates 20, a plurality of inverters 21a-c, and a plurality of FETs 22a,b. For ease of illustration, only one NAND gate 20, and one of each set of inverters 21a-c is shown. However, as illustrated in FIG. 3, the notation 10X denotes a set of 10 components of each selected minimum unit value type, and the notation 2X denotes a set of 2 components of the selected minimum value type. That is, the 2X and 10X notations in FIG. 3 are placed there to indicate the relative size of each device that can be referenced to a minimum unit device.
Therefore, in the conventional output structure, a two-input NAND gate 20 receives as its inputs, input signals A and EN. NAND gate 20 is connected in series with a first inverter 21a which is connected in series with a second inverter 21b to form a buffer. The output of the second inverter 21b is provided to the gate terminal of FET 22a. The source terminal of FET 22a is connected with voltage source V.sub.DD.
Inverter 21c receives as its input, signal EN. The output of the inverter 21c is provided to the gate terminal of FET 22b. The source terminal of FET 22b is connected with voltage source V.sub.DD. The drain terminals of FETs 22a,b are connected together, which provide output signal Z.
However, these conventional CMOS-PECL drivers fail to deliver a tightly controlled output level under different operating conditions and over wide-tolerance manufacturing process specifications.
Most of the known conventional circuits which attempt a solution to this problem are of the analog, feedback type. These circuits monitor and/or sense either PECL driver outputs or a dummy replica input/output (I/O) structure and then compare them with either internal and/or external preset reference voltages V.sub.OL and V.sub.OH, and generate bias voltages for the actual I/O structures.